The present invention relates to a vertical transistor of a semiconductor device and a method of forming the same and, more particularly, to a vertical transistor of a semiconductor device, which has channel areas formed in a vertical direction to a semiconductor substrate, and a method of forming the same.
Semiconductor devices have been developed in various forms in order to facilitate high integration. As part of such efforts, a vertical transistor has been proposed.
FIG. 1 shows conventional semiconductor poles. As seen in FIG. 1, each of semiconductor poles 12 includes an upper portion 12a having a first width W1 and a lower portion 12b having a second width W2 narrower than the first width W1. The semiconductor poles 12 are isolated by a trench 14 formed in the semiconductor substrate 10. The lower portion 12b of the semiconductor pole 12 corresponds to a channel area, and the height of the lower portion 12b corresponds to a channel length. In order to prevent a short channel effect in the transistor, it is preferred that the lower portion 12b of the semiconductor pole be high. However, if the lower portion 12b of the semiconductor pole is high, the lower portion 12b of the semiconductor pole cannot withstand the load of the upper portion 12a and the load applied thereto when subsequent processes are performed. Consequently, a problem arises because the semiconductor poles 12 collapse or are inclined as in a region ‘A’ shown in FIG. 2.
Further, since a top width of the trench 14 is narrower than a lower width thereof, the trench 14 is not fully gap-filled with a conductive layer when the trench 14 is gap-filled with the conductive layer in order to form a gate electrode. Accordingly, a seam may occur at the bottom of the trench 14. The semiconductor substrate 10 corresponding to a portion where the seam is generated is exposed to etch materials and likely to be damaged, when an etch process for forming the gate electrode is performed.